ATA8742-PXQW【PDF 136/238 页】MCU W/TRANSMITTER ASK/FSK 24QFN

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Sheet目录52

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136

9151AINDCO07/09

ATA8742

22. Timer/Counter Prescaler

Timer/Counter 0, and 1 share the same prescaler module, but the Timer/Counters can have dif-

ferent prescaler settings. The description below applies to all Timer/Counters. Tn is used as a

general name, n = 0, 1.

The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This

provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system

clock frequency (f

CLK_I/O

). Alternatively, one of four taps from the prescaler can be used as a

clock source. The prescaled clock has a frequency of either f

CLK_I/O

/8, f

CLK_I/O

/64, f

CLK_I/O

/256, or

CLK_I/O

/1024.

22.0.1

Prescaler Reset

The prescaler is free running, i.e., operates independently of the Clock Select logic of the

Timer/CounterCounter, and it is shared by the Timer/Counter Tn. Since the prescaler is not

affected by the Timer/Counters clock select, the state of the prescaler will have implications for

situations where a prescaled clock is used. One example of prescaling artifacts occurs when the

timer is enabled and clocked by the prescaler (6 > CSn2:0 > 1). The number of system clock

cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system

clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).

It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to program

execution.

22.0.2

External Clock Source

An external clock source applied to the Tn pin can be used as Timer/Counter clock (clk

). The

Tn pin is sampled once every system clock cycle by the pin synchronization logic. The synchro-

nized (sampled) signal is then passed through the edge detector. Figure 22-1 on page 136

shows a functional equivalent block diagram of the Tn synchronization and edge detector logic.

The registers are clocked at the positive edge of the internal system clock (clk

I/O

). The latch is

transparent in the high period of the internal system clock.

The edge detector generates one clk

pulse for each positive (CSn2:0 = 7) or negative (CSn2:0

= 6) edge it detects.

Figure 22-1. T0 Pin Sampling

The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles

from an edge has been applied to the Tn pin to the counter is updated.

Enabling and disabling of the clock input must be done when Tn has been stable for at least one

system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.

Each half period of the external clock applied must be longer than one system clock cycle to

ensure correct sampling. The external clock must be guaranteed to have less than half the sys-

Tn_sync

(To Clock

Select Logic)

Edge Detector

Synchronization

D Q

clk

I/O

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